The present invention relates to a nonvolatile semiconductor memory with an electrically erasing and programming (or reprogramming) function, and more specifically to a nonvolatile semiconductor memory that has realized enhanced speed of reprogramming nonvolatile semiconductor memory cells driven by a single external supply voltage and of verifying the state of the reprogrammed memory cells and which has also realized a substantial reduction in the size of the memory.
In a nonvolatile semiconductor memory, in which a group of memory cells (hereinafter referred to as a sector) arranged in array and connected to a common control gate line, i.e., a common word line, are electrically erased and programmed (or reprogrammed), a method has been proposed to erase the memory cells a word line at a time by applying a negative voltage to the word lines. This method is described, for example, in Symposium on VLSI Technology Digest of Technical Papers, pp77-78 1991 and Symposium on VLSI Circuits Digest of Technical Papers, pp85-86 1991. Further, a method of programming that applies a negative potential to a word line is introduced in Technical Digest of International Electron Device Meeting, pp.599-602 1992 and 991-993 1992.
In this programming and erasing method, a technique has been proposed in which a word decoder circuit that drives word lines is constructed in a hierarchical configuration, consisting of a main decoder circuit and a subword decoder circuit. This technique is described in International Solid-State Circuits Conference Digest of Technical Papers, pp154-155 1992; Symposium on VLSI Circuits Digest of Technical Papers pp97-98 1993; and Symposium on VLSI Circuits Digest of Technical Papers pp99-100 1993.
FIGS. 17, 18 and 19 show subword decoder circuits used in the above-mentioned conventional memory devices. The subword decoder circuits shown in FIGS. 17 and 18 consist of one p-channel transistor and two n-channel transistors; and the circuits shown in FIG. 19 consist of two p-channel transistors and two n-channel transistors. In these circuits, denoted W11-W1j are word lines.
The conventional subword decoder circuits (WD11, WD1j) shown in FIG. 17 take in as inputs a block selection address line Bip Generated from a first address line Group and its complementary address line BBip and in-block selection lines Gaj, GBj, GCj Generated from a second address line Group. In the figure, designated VPM is a substrate voltage of the p-channel transistor, and VER is a substrate voltage and a source potential of an n-channel transistor. The conventional subword decoder circuits of FIG. 18 take in as inputs a block selection address line Bip and its complementary address line BBip and an in-block selection line Gj. The conventional circuits of FIG. 19 take in as inputs a block selection address line Bip and its complementary address line BBip and an in-block selection line Gj. Denoted VNN is a substrate voltage of the n-channel transistor.
In the conventional subword decoder circuits shown in FIG. 17, 18 and 19, the erasing and programming operation that lowers the threshold value of the memory cell is performed by applying a negative voltage supplied from the source side of the n-channel transistor to a word line. For example, in the circuit of FIG. 17, setting GC1 to a negative voltage (Bip=0 V, BBip=5 V, GC1=-13 V, GC2-GCj=0 V, GA1-GAj=0 V, GB1-GBj=-13 V, VPM=5 V, VER=-13 V) applies a negative voltage to the word line W11.
With the word line applied a negative voltage, electrons in a floating gate of a memory cell connected to the word line are discharged, lowering the threshold value of the memory cell. In these nonvolatile semiconductor memory devices, after the reprogram operation that lowers the threshold value of the memory cell, an operation to check the threshold value of the memory cell or a verify operation is performed. This verify operation is described, for example, in International Solid-State Circuits Conference Digest of Technical Papers pp60-61 1990. This operation checks the threshold value of a memory cell by applying a positive voltage (verify voltage) lower than the supply voltage to a word line to decide whether or not a current flows into the memory cell.
In the conventional circuits shown in FIGS. 17, 18 and 19, the verify voltage applied to a word line is supplied from the source side of the p-channel transistor. In the circuit of FIG. 17, for instance, setting the line Bip to a positive voltage lower than the supply voltage causes a verify voltage to be applied to a word line (Bip=3.6 V, BBip=0 V, GA1=0 V, GA2-GAj=3.6 V, GB1=0 V, GB2-GBj=3.6 V, GC1-GCj=0 V, VPM=3.6 V, VER=0 V).
Another example of the conventional subword decoder circuit that drives the word line is found in Japanese Patent Laid-Open No. 174595/1993. FIG. 20 shows a conventional subword decoder circuit formed of an inverter circuit.
The conventional subword decoder circuits shown in FIG. 20 (WD11, WD1j) consist of one p-channel transistor and one n-channel transistor, with a common drain of each transistor connected to a word line (W11-W1j). A block selection address line generated from the first address line group is applied to the source of the p-channel transistor and an in-block selection line Gj generated from the second address line group is applied to a common gate of these transistors. The source potential of the n-channel transistor is always at the ground potential Vss.
In this circuit, a potential that can be applied to the word line includes a positive voltage of the block selection address line Bip (for example, a supply voltage Vcc or a high voltage Vpp) and the ground voltage Vss.